Thermocompression for semiconductor chip assembly

ABSTRACT

An assembly of a semiconductor chip having pads to a substrate having pads aligned to receive the semiconductor chip is provided, whereby at least one of the semiconductor chip pads and substrate pads include solder bumps. The solder bumps are deformed against the substrate pads and the semiconductor chip pads, whereby an underfill material is applied to fill the gap between the semiconductor chip and substrate such that the underfill material envelopes both the deformed solder bumps and the substrate pads. The underfill material does not penetrate between the deformed solder bumps, the semiconductor chip pads, and the substrate pads based on a compression force causing the solder bumps to be deformed against the substrate pads and the semiconductor chip pads. At least one of the solder bumps have not been melted or reflowed to make a metallurgical bond between the semiconductor chip pads and the substrate pads.

BACKGROUND

The present exemplary embodiments relate to the joining of semiconductorchips to substrates to form semiconductor packages and, moreparticularly, relate to the thermocompression of solder bumps for atemporary mechanical join between the semiconductor chip and thesubstrate pads prior to the dispensing of an underfill material.

In a typical assembly process, a semiconductor chip is aligned with thepads on a substrate and then the solder bumps on the semiconductor chipare heated to cause reflow of the solder bumps and form a metallurgicaljoin to the substrate pads. An underfill material may then be dispensedbetween the semiconductor chip and substrate.

A simpler process would be desirable that is suitable for a high volumemanufacturing operation.

BRIEF SUMMARY

The various advantages and purposes of the exemplary embodiments asdescribed above and hereafter are achieved by providing, according to afirst aspect of the exemplary embodiments, a method of assembling asemiconductor chip to a substrate including: providing a semiconductorchip having pads; providing a substrate having pads to receive thesemiconductor chip; providing solder bumps on at least one of thesemiconductor chip pads and substrate pads; aligning the semiconductorchip pads with the substrate pads; applying a compression force to thesemiconductor chip to cause the solder bumps to deform against, and makecontact with, the substrate pads and the semiconductor chip pads, thecompression force being applied while the semiconductor chip andsubstrate are held at a temperature above room temperature and below atemperature at which any liquid will form in at least one of the solderbumps; after applying a compression force, applying an underfillmaterial to fill the gap between the semiconductor chip and thesubstrate, the underfill material not penetrating between the deformedsolder bumps, the semiconductor chip pads and the substrate pads; andafter applying the underfill material, heating the assembledsemiconductor chip and substrate to an elevated temperature to cause thesolder bumps to melt and reflow and form a plurality of metallurgicalbonds between the semiconductor chip pads and the substrate pads.

According to a second aspect of the exemplary embodiments, there isprovided a method of assembling a semiconductor chip having pads to asubstrate having pads to receive the semiconductor chip, at least one ofthe semiconductor chip pads and substrate pads having solder bumps. Themethod including: aligning the semiconductor chip with the substrate;applying a compression force to the semiconductor chip to cause thesolder bumps to deform against, and make contact with, the substratepads and the semiconductor chip pads, the compression force beingapplied while the semiconductor chip and substrate are held at atemperature above room temperature and below a temperature at which anyliquid will form in at least one of the solder bumps; performing anelectrical test on the semiconductor chip or substrate that requires atleast one electrical function of the semiconductor chip to befunctional; after performing an electrical test, applying an underfillmaterial to fill the gap between the substrate and the semiconductorchip, the underfill material not penetrating between the deformed solderbumps, the semiconductor chip pads and substrate pads; and afterapplying an underfill material, heating the assembled semiconductor chipand substrate to an elevated temperature to cause the solder bumps tomelt and reflow and form a metallurgical bond between the semiconductorchip pads and the substrate pads.

According to a third aspect of the exemplary embodiments, there isprovided an assembly of a semiconductor chip having pads to a substratehaving pads aligned to receive the semiconductor chip, at least one ofthe semiconductor chip pads and substrate pads having solder bumps, thesolder bumps being deformed against the substrate pads and thesemiconductor chip pads, an underfill material applied to fill the gapbetween the semiconductor chip and substrate such that the underfillmaterial does not penetrate between the deformed solder bumps, thesemiconductor chip pads and substrate pads, wherein at least one of thesolder bumps have not been melted or reflowed to make a metallurgicalbond between the semiconductor chip and the substrate pads.

BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS

The features of the exemplary embodiments believed to be novel and theelements characteristic of the exemplary embodiments are set forth withparticularity in the appended claims. The Figures are for illustrationpurposes only and are not drawn to scale. The exemplary embodiments,both as to organization and method of operation, may best be understoodby reference to the detailed description which follows taken inconjunction with the accompanying drawings in which:

FIGS. 1A to 1E are partial cross-sectional views illustrating apreferred sequence of processes for practicing the exemplaryembodiments.

FIG. 2 is a side view of a deformed solder bump after thermocompressionaccording to the exemplary embodiments.

FIG. 3 is a flow chart of a method for practicing the exemplaryembodiments.

FIGS. 4A to 4F are partial cross-sectional views illustrating variousexemplary embodiments of the solder bumps with respect to thesemiconductor chip and the substrate pads.

DETAILED DESCRIPTION

Referring to FIGS. 1A to 1E in more detail, and particularly referringto FIG. 1A, there is shown a semiconductor chip 10 having input/output(I/O) pads 11 and solder bumps 12 and a substrate 14 having pads 16. Thepads 16 may include connection pads 20 and solder bumps 18. As will beexplained hereafter, in some exemplary embodiments, the I/O pads 11 maynot include the solder bumps 12 and, further, the pads 16 may justinclude the connection pads 20 or alternatively, the pads 16 may includesolder bumps 18 as well.

The substrate 14 may include any substrate in use today or in the futureincluding ceramic substrates; Flip Chip Ball Grid Array (FCBGA)substrates constructed by laminating a dielectric, copper and fiberglasslayers; plastic substrates, fiberglass/epoxy substrates (FR-4), etc.

In practice, the solder bumps 12 of semiconductor chip 10 are alignedwith pads 16 of substrate 14. During the alignment process in FIG. 1A,it may be desirable to heat the semiconductor chip 10 and substrate 14to about 150° C. (or higher, as long as the solder bumps 12, 18 on thesemiconductor chip 10 and the substrate 14 do not all melt or form aliquid).

When semiconductor chip 10 is aligned with substrate 14 so that solderbumps 12 are just touching pads 16, the semiconductor chip 10 andsubstrate 14 may be separated by a distance D1.

While solder bumps 12 are shown touching pads 16 in FIG. 1A for thepurpose of illustrating distance D1, the solder bumps 12 and pads 16 maynot actually touch during alignment.

Referring now to FIG. 1B, the semiconductor chip 10 and substrate 14 areheated to an elevated temperature in the range of 150° C. to atemperature that is just below the temperature at which liquid will formin the solder of the semiconductor chip bumps 12 or substrate pads 16.That is, liquid may form in the solder of some of the semiconductor chipbumps 12 or liquid may form in the solder of some of the substrate pads16 but liquid may not form in all bumps, so that at least two bumps arecompressed against each while in a solid state. It is also within thescope of the exemplary embodiments for liquid to form in neither of thesemiconductor chips bumps 12 or substrate pads 16 so long as thetemperature is high enough to soften the solder bumps. For eutecticsolders, the high point of the temperature range will be just below theeutectic point and for non-eutectic solders, the high point of thetemperature range will be just below the solidus. The solidus is a curveon a phase diagram of the solder below which a solder is completelysolid.

While heated, a suitable compression force, indicated by arrows 22, of 5to 25 grams per solder bump may be applied to cause the solder bumps 12to deform against the pads 16. The amount of compression force may bevaried to adjust the final shape of the solder bumps 12 and pads 16 toform a temporary mechanical join. Lower compression forces may be usedfor the same final shape if higher temperatures or longer compressiontimes are used.

After application of the compression force 22, the semiconductor chip 10and substrate 14 are now separated by a distance D2 where D2 is lessthan D1. In a preferred exemplary embodiment, D2 may 5 to 75% of D1 andin a most preferred embodiment, D2 may be 25 to 50% of D1.

FIG. 2 schematically illustrates the solder bumps 12 and pads 16 aftercompression. Where the solder bumps 12 and pads 16 had a substantiallyhemispherical shape as shown in FIG. 1A, the solder bumps 12 and pads 16are now deformed and flattened. Between the solder bumps 12 and pads 16is a thin interface 24. While the solder bumps 12 and pads 16 are now injust mechanical contact, the interface 24 is sufficiently tight suchthat the underfill which is dispensed in a subsequent step cannotpenetrate the interface 24 by capillarity. While it is believed there isno metallurgical join formed between the solder bumps 12 and pads 16,there is some sticking together of the solder bumps 12 and pads 16 suchthat if the semiconductor chip 10 is pulled apart from the substrate 14after compression 22, there is some force required to pull thesemiconductor chip 10 and substrate 14 apart. This force may simplyarise from some mechanical interlocking of the solder bumps 12 and pads16 together, although it is not known at this time whether otherphysical or chemical mechanisms may be activated in this process toincrease the bonding force.

Returning back to FIG. 1B, the compression force 22 is preferablyapplied for only about 1 second to cause deformation of the solder bumps12 and pads 16. Much longer hold times may not offer any advantages,although in some cases hold times of 5 seconds or more might be used.

Referring now to FIG. 1C, the assembly of semiconductor chip 10 andsubstrate 14 may be cooled to about 110° C. and then a conventionalunderfill material 26 may be dispensed into the gap volume between thesemiconductor chip 10 and substrate 14 so as to envelop the solder bumps12 and pads 16. An example of a conventional underfill material might bean epoxy resin filled with small silica spheres. Even though there is noapparent metallurgical bond between the solder bumps 12 and pads 16,there is no or very little penetration of underfill material 26 intointerface 24 (FIG. 2) between solder bumps 12 and pads 16.

The underfill material 26 may be cured at a temperature suitable for theunderfill material 26 as indicated in FIG. 1D. One such temperature maybe around 150° C.

Referring now to FIG. 1E, the assembled semiconductor chip 10 andsubstrate 14 undergo a reflow operation to melt the solder bumps 12 andpads 16 and form a metallurgical bond. A solder flux is unnecessary forthe reflow process although a flux may be added earlier, such as beforethe application of the compression force 22, to improve the rate offormation of the metallurgical bond. An advantage of the exemplaryembodiments is that if there is included a cap 28 over the semiconductorchip 10, the reflow of the solder bumps 12 and pads 16 may occur afterthe cap 28 is attached. A further advantage of the exemplary embodimentsis that if solder balls 30 are added to the substrate 14, the reflow ofthe solder bumps 12 and pads 16 may occur at the same time as the reflowof the solder balls 30.

Referring now to FIG. 3, there is illustrated a flow chart of a methodfor practicing the exemplary embodiments. Processes that are outlined indotted lines are optional processes. In a first optional process, box302, the substrate may be planarized. Planarizing may be by, forexample, pressing a flat, heated surface against the solder bumps of thepads so as to impart a flat surface to the solder bumps.

In another optional process, box 304, the solder bumps on thesemiconductor chip may be planarized by, for example, pressing a flat,heated surface against the solder bumps so as to impart a flat surfaceto the solder bumps.

In yet another optional process, box 306, the semiconductor chip andsubstrate may be cleaned, for example, by a plasma process to reduce oreliminate any contaminant on the surface of the semiconductor chip, thesubstrate, the pads or the solder. The plasma process may also have apositive impact on the flow or the adhesion of the capillary underfill.An example of a plasma process is exposing the components to areactive-ion etching (RIE) low-pressure oxygen plasma for about 30seconds.

Next, box 308, the semiconductor chip and substrate may be aligned asdescribed previously with respect to FIG. 1A. A tacking agent such as apolymeric material may be used to maintain the alignment in thefollowing processes.

A compression force may then be applied to the semiconductor chip andsubstrate to cause deformation of the solder bumps on the semiconductorchip and deformation of the pads on the substrate, box 310, as alsodescribed previously with respect to FIG. 1B.

It may be desirable to test, electrically or otherwise, the assembledsemiconductor chip and substrate, box 312. The solder bumps on thesemiconductor chip and the pads on the substrate may be in sufficientlygood mechanical contact after the compression process described abovesuch that an electrical test may be conducted through the solder bumpson the semiconductor chip and the pads on the substrate. It may not benecessary to have 100% electrical continuity as substantial electricalcontinuity (less than 100% electrical continuity) between one of thesemiconductor chip pads and one of the substrate pads may be sufficientfor certain types of testing. Additional testing may include testing theintrinsic functionality of the semiconductor chip and substrate.

If after the testing just described, it is determined that thesemiconductor chip or substrate are defective, either may be easilyreplaced in a reworking process by separating the semiconductor chipfrom the substrate and then starting the process over, such as byplanarizing the substrate or the solder bumps on the semiconductor chipor by aligning the semiconductor chip and substrate.

Next, underfill material may be dispensed as indicated in box 316followed by curing the underfill in box 318.

In an optional process, box 320, a cap or solder balls may be attachedas described previously with respect to FIG. 1E.

Lastly, there is solder reflow, box 322, of the semiconductor chipsolder bumps and the substrate pads. If there are solder balls, such assolder balls 30 in FIG. 1E, the solder balls may also be reflowed atthis time.

Referring now to FIGS. 4A to 4F, there are illustrated various exemplaryembodiments of the solder bumps with respect the semiconductor chip andthe pads on the substrate.

In the various other embodiments shown in FIGS. 4A to 4F, the solderbumps may be on the semiconductor chip only, the substrate only or boththe semiconductor chip and substrate. Then, the solder bumps aredeformed between the semiconductor chip and substrate so as to makecontact with the semiconductor chip I/O pads and substrate connectionpads.

Any solder may be used in the exemplary embodiments including leadedsolders and, more preferably, lead-free solders.

The temperature during compression in these various other embodimentsmay be such as to avoid the formation of liquid in the solder bumps ifthey are only on the semiconductor chip or only on the substrate. If thesolder bumps are on both the semiconductor chip and substrate, thetemperature during compression may be such as to avoid the formation ofliquid in both the solder bumps on the semiconductor chip and the solderbumps on the substrate.

In FIG. 4A, solder bumps 12A joined to I/O pads 11A on semiconductorchip 10 and/or solder bumps 18A joined to connection pads 20A onsubstrate 14 may be planarized by, for example, pressing a flat, heatedsurface on the solder bumps 12A or 18A. Solder bumps 12A and/or 18A nowhave a flat surface which may facilitate the method of the exemplaryembodiments.

Alternatively, as shown in FIG. 4B, the solder bumps on substrate 14 maybe dispensed with so that solder bumps 12B on semiconductor chip 10 arejoined directly to substrate connection pads 20B.

In place of the solder bumps on semiconductor chip 10, there may becopper pillars 32 joined to I/O pads 11C and having solder bumps 12C onthe ends of the copper pillars 32 as shown in FIG. 4C. The solder bumps12C may be joined directly to connection pads 20C.

In another exemplary embodiment as shown in FIG. 4D, solder bumps 12D oncopper pillars 32 may be joined to solder bumps 18D on connection pads20D.

In a further exemplary embodiment as shown in FIG. 4E, there may besolder bumps 18E only on substrate connection pads 20E so that thesemiconductor chip 10 is joined directly to solder bumps 18E.Semiconductor chip 10 may have I/O pads 11E for receiving the solderbumps 18E.

In yet another exemplary embodiment as shown in FIG. 4F, semiconductorchip 10 may have copper pillars 32 but in this exemplary embodiment,there are only solders bumps 18F on substrate connection pads 20F.

Included within the exemplary embodiments is an assembly of asemiconductor chip having pads to a substrate having pads aligned toreceive the semiconductor chip. At least one of the semiconductor chippads and substrate pads have solder bumps. The solder bumps are deformedagainst the substrate pads and the semiconductor chip pads. An underfillmaterial may be applied to fill the gap between the semiconductor chipand substrate such that the underfill material does not penetratebetween the deformed solder bumps, the semiconductor chip pads and thesubstrate pads. At least one of the solder bumps between thesemiconductor chip pads and substrate pads have not been melted orreflowed to make a metallurgical bond between the semiconductor chippads and the substrate pads.

The assembly of the semiconductor chip and substrate may include any ofthe embodiments disclosed in FIGS. 1A to 1E and FIGS. 4A to 4F.

It will be apparent to those skilled in the art having regard to thisdisclosure that other modifications of the exemplary embodiments beyondthose embodiments specifically described here may be made withoutdeparting from the spirit of the invention. Accordingly, suchmodifications are considered within the scope of the invention aslimited solely by the appended claims.

1.-24. (canceled)
 25. An assembly of a semiconductor chip having pads toa substrate having pads aligned to receive the semiconductor chip, atleast one of the semiconductor chip pads and substrate pads havingsolder bumps, the solder bumps being deformed against the substrate padsand the semiconductor chip pads, an underfill material applied to fillthe gap between the semiconductor chip and substrate such that theunderfill material envelopes both the deformed solder bumps and thesubstrate pads, the underfill material not penetrating between thedeformed solder bumps, the semiconductor chip pads, and the substratepads based on a compression force causing the solder bumps to bedeformed against the substrate pads and the semiconductor chip pads,wherein at least one of the solder bumps have not been melted orreflowed to make a metallurgical bond between the semiconductor chippads and the substrate pads.
 26. The assembly of claim 25, wherein thesemiconductor chip further comprises copper pillars extending from thesemiconductor chip pads and the solder bumps are between the ends of thecopper pillars and the substrate pads.
 27. The assembly of claim 25,wherein only the substrate comprises solder bumps.
 28. The assembly ofclaim 25, wherein only the semiconductor chip comprises solder bumps.29. The assembly of claim 25, wherein the semiconductor chip andsubstrate both comprise solder bumps.
 30. The assembly of claim 29,further comprising solder bumps on the substrate pads.
 31. The assemblyof claim 25, wherein the semiconductor chip further comprises copperpillars extending from the semiconductor chip pads, the copper pillarsbeing devoid of solder bumps, and the solder bumps are on the substrate.